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256k x 36/512k x 18 pipelined sram with nobl? architecture cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05161 rev. *b revised april 25, 2002 features ? zero bus latency, no dead cycles between write and read cycles fast clock speed: 200, 166, 133, 100 mhz fast access time: 3.2, 3.6, 4.2, 5.0 ns internally synchronized registered outputs eliminate the need to control oe single 3.3v ?5% and +5% power supply v cc separate v ccq for 3.3v or 2.5v i/o single wen (read/write) control pin positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications interleaved or linear four-word burst capability individual byte write (bwa ?bwd ) control (may be tied low) cen pin to enable clock and suspend operations three chip enables for simple depth expansion automatic power-down feature available using zz mode or ce select jtag boundary scan low-profile 119-bump, 14-mm 22-mm bga (ball grid array), and 100-pin tqfp packages functional description the cy7c1354a/gvt71256zc36 and cy7c1356a/ gvt71512zc18 srams are designed to eliminate dead cycles when transitioning from read to write or vice versa. these srams are optimized for 100% bus utilization and achieve zero bus latency ? (zbl ? )/no bus latency ? (nobl ? ). they integrate 262,144 36 and 524,288 18 sram cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. these employ high-speed, low-power cmos designs using advanced triple-layer polysilicon, double-layer metal technology. each memory cell consists of four transistors and two high-valued resistors. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, depth-expansion chip enables (ce , ce 2 , and ce 3 ), cycle start input (adv/ld ), clock enable (cen ), byte write enables (bwa , bwb , bwc , and bwd ), and read-write control (wen ). bwc and bwd apply to cy7c1354a/gvt71256zc36 only. address and control signals are applied to the sram during one clock cycle, and two cycles later, its associated data occurs, either read or write. a clock enable (cen ) pin allows operation of the cy7c1354a/gvt71256zc36/cy7c1356a/gvt71512zc18 to be suspended as long as necessary. all synchronous inputs are ignored when (cen ) is high and the internal device registers will hold their previous values. there are three chip enable pins (ce , ce 2 , ce 3 ) that allow the user to deselect the device when desired. if any one of these three are not active when adv/ld is low, no new memory operation can be initiated and any burst cycle in progress is stopped. however, any pending data transfers (read or write) will be completed. the data bus will be in high-impedance state two cycles after chip is deselected or a write cycle is initiated. the cy7c1354a/gvt71256zc36 and cy7c1356a/ gvt71512zc18 have an on-chip two-bit burst counter. in the burst mode, the cy7c1354a/gvt71256zc36 and cy7c1356a/gvt71512zc18 provide four cycles of data for a single address presented to the sram. the order of the burst sequence is defined by the mode input pin. the mode pin selects between linear and interleaved burst sequence. the adv/ld signal is used to load a new external address (adv/ld = low) or increment the internal burst counter (adv/ld = high) output enable (oe ), sleep enable (zz) and burst sequence select (mode) are the asynchronous signals. oe can be used to disable the outputs at any given time. zz may be tied to low if it is not used. four pins are used to implement jtag test capabilities. the jtag circuitry is used to serially shift data to and from the device. jtag inputs use lvttl/lvcmos levels to shift data during this testing mode of operation. selection guide 7c1354a-200 71256zc36-5 7c1356a-200 71512zc18-5 7c1354a-166 71256zc36-6 7c1356a-166 71512zc18-6 7c1354a-133 71256zc36-7.5 7c1356a-133 71512zc18-7.5 7c1354a-100 71256zc36-10 7c1356a-100 71512zc18-10 unit maximum access time 3.2 3.6 4.2 5.0 ns maximum operating current commercial 560 480 410 350 ma maximum cmos standby current commercial 30 30 30 30 ma
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 2 of 31 . note: 1. the functional block diagram illustrates simplified device operation. see truth table, pin descriptions, and timing diagrams for detailed information. 1m x 9 x 2 sram array dqa, dqb clk input registers mux output registers output buffers address control di do sel control logic oe# zz mode cke# adv/ld# r/w# bwa#, bwb# ce#, ce2#, ce2 sa0, sa1, sa oe cen adv/ld wen bw a, bw b ce , ce 2 , ce 3 cen a0, a1, a functional block diagram ? 256k 36 [1] 256k x 9 x 4 sram array dqa-dqd clk input registers mux output registers output buffers address control di do sel control logic oe# zz mode cke# adv/ld# r/w# bwa#, bwb# bwc#, bwd# ce#, ce2#, ce2 sa0, sa1, sa functional block diagram ? 512k 18 [1] cen adv/ld wen bw a, bw b, ce , ce 2 , ce 3 cen bw c, bw d oe input registers a0, a1, a
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 3 of 31 pin configurations a a a a a1 a0 tms tdi v ss v cc tck a a a a a a v ccq v ss dqb dqb dqb v ss v ddq dqb dqb v ss v cc v cc dqa dqa v ccq v ss dqa dqa v ss v ccq v ccq v ss dqc dqc v ss v ccq dqc dqc v cc v ss dqd dqd v ccq v ss dqd dqd dqd v ss v ddq a a ce ce 2 bwa ce 3 v cc v ss clk wen cen oe nc a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz tdo cy7c1354a/ 100-lead tqfp packages a a a a a1 a0 tms tdi v ss v cc tck a a a a a a a nc nc v ccq v ss nc dqa dqa dqa v ss v ccq dqa dqa v ss v cc v cc dqa dqa v ccq v ss dqa dqa nc nc v ss v ccq nc nc nc nc nc nc v ccq v ss nc nc dqb dqb v ss v ccq dqb dqb v cc v ss dqb dqb v ccq v ss dqb dqb dpb nc v ss v ccq nc nc nc a a ce ce 2 nc nc bwb bwa ce 3 v cc v ss clk wen cen oe nc a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode tdo cy7c1356a/ bwd mode bwc dqc dqc dqc dqc dqc dqd dqd dqd dqd dqb dqb dqa dqa dqa dqa dqa dqb dqb (256k 36) (512k 18) bwb v cc v cc v cc gvt71256zc36 gvt71512zc18 v cc
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 4 of 31 pin configurations (continued) cy7c1354a/gvt71256zc36 (256k 36) ? 7 17 bga 119-ball bump bga cy7c1356a/gvt71512zc18 (512k 18) ? 7 17 bga 1234567 a v ccq aancaav ccq b nc ce 2 aadv/ld ace 3 nc c nc a a v cc aanc d dqc dqc v ss nc v ss dqb dqb e dqc dqc v ss ce v ss dqb dqb f v ccq dqc v ss oe v ss dqb v ccq g dqc dqc bwc abwb dqb dqb h dqc dqc v ss wen v ss dqb dqb j v ccq v cc nc v cc nc v cc v ccq k dqd dqd v ss clk v ss dqa dqa l dqd dqd bwd nc bwa dqa dqa m v ccq dqd v ss cen v ss dqa v ccq n dqd dqd v ss a1 v ss dqa dqa p dqd dqd v ss a0 v ss dqa dqa r nc a mode v cc v ss anc t nc nc a a a nc zz u v ccq tms tdi tck tdo nc v ccq 1234567 a v ccq aancaav ccq b nc ce 2 aadv/ld ace 3 nc c nc a a v cc aanc d dqb nc v ss nc v ss dqa nc e nc dqb v ss ce v ss nc dqa f v ccq nc v ss oe v ss dqa v ccq g nc dqb bwb av ss nc dqa h dqb nc v ss wen v ss dqa nc j v ccq v cc nc v cc nc v cc v ccq k nc dqb v ss clk v ss nc dqa l dqb nc v ss nc bwa dqa nc m v ccq dqb v ss cen v ss nc v ccq n dqb nc v ss a1 v ss dqa nc p nc dqb v ss a0 v ss nc dqa r nc a mode v cc v cc anc t ncaancaazz u v ccq tms tdi tck tdo nc v ccq
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 5 of 31 pin descriptions ? 256k 36 256k 36 tqfp pins 256k 36 pbga pins pin name type pin description 37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 83, 99, 100 4p 4n 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 4g, 2r, 6r, 3t, 4t, 5t a0, a1, a input- synchronous synchronous address inputs : the address register is triggered by a combination of the rising edge of clk, adv/ld low, cen low and true chip enables. a0 and a1 are the two least significant bits (lsbs) of the address field and set the internal burst counter if burst cycle is initiated. 93, 94, 95, 96 5l 5g 3g 3l bwa , bwb , bwc , bwd input- synchronous synchronous byte write enables : each nine-bit byte has its own active low byte write enable. on load write cycles (when wen and adv/ld are sampled low), the appropriate byte write signal (bwx ) must be valid. the byte write signal must also be valid on each cycle of a burst write. byte write signals are ignored when wen is sampled high. the appropriate byte(s) of data are written into the device two cycles later. bwa controls dqa pins; bwb controls dqb pins; bwc controls dqc pins; bwd controls dqd pins. bwx can all be tied low if always doing writes to the entire 36-bit word. 87 4m cen input- synchronous synchronous clock enable input : when cen is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. the effect of cen sampled high on the device outputs is as if the low-to-high clock transition did not occur. for normal operation, cen must be sampled low at rising edge of clock. 88 4h wen input- synchronous read write : wen signal is a synchronous input that identifies whether the current loaded cycle and the subsequent burst cycles initiated by adv/ld is a read or write operation. the data bus activity for the current cycle takes place two clock cycles later. 89 4k clk input- synchronous clock : this is the clock input to cy7c1354a/gvt71256zc36. except for oe , zz and mode, all timing references for the device are made with respect to the rising edge of clk. 98, 92 4e, 6b ce , ce 3 input- synchronous synchronous active low chip enable : ce and ce 3 are used with ce 2 to enable the cy7c1354a/gvt71256zc36. ce or ce 3 sampled high or ce 2 sampled low, along with adv/ld low at the rising edge of clock, initiates a deselect cycle. the data bus will be high-z two clock cycles after chip deselect is initiated. 97 2b ce 2 input- synchronous synchronous active high chip enable : ce 2 is used with ce and ce 3 to enable the chip. ce 2 has inverted polarity but otherwise is identical to ce and ce 3 . 86 4f oe input asynchronous output enable : oe must be low to read data. when oe is high, the i/o pins are in high-impedance state. oe does not need to be actively controlled for read and write cycles. in normal operation, oe can be tied low. 85 4b adv/ ld input- synchronous advance/load : adv/ld is a synchronous input that is used to load the internal registers with new address and control signals when it is sampled low at the rising edge of clock with the chip is selected. when adv/ld is sampled high, then the internal burst counter is advanced for any burst that was in progress. the external addresses and wen are ignored when adv/ld is sampled high. 31 3r mod e input- static burst mode : when mode is high or nc, the interleaved burst sequence is selected. when mode is low, the linear burst sequence is selected. mode is a static dc input. 64 7t zz input- asynchronous sleep enable : this active high input puts the device in low power consumption standby mode. for normal operation, this input has to be either low or nc.
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 6 of 31 51, 52, 53, 56- 59, 62, 63 68, 69, 72-75, 78, 79, 80 1, 2, 3, 6-9, 12, 13 18, 19, 22-25, 28, 29, 30 (a) 6p, 7p, 7n, 6n, 6m, 6l, 7l, 6k, 7k, (b) 7h, 6h, 7g, 6g, 6f, 6e, 7e, 7d, 6d, (c) 2d, 1d, 1e, 2e, 2f, 1g, 2g, 1h, 2h, (d) 1k, 2k, 1l, 2l, 2m, 1n, 2n, 1p, 2p dqa dqb dqc dqd input/ output data inputs/outputs : both the data input path and data output path are registered and triggered by the rising edge of clk. byte ? a ? is dqa pins; byte ? b ? is dqb pins; byte ? c ? is dqc pins; byte ? d ? is dqd pins. 38 39 43 2u 3u 4u tms tdi tck input ieee 1149.1 test inputs : lvttl-level inputs. if serial boundary scan (jtag) is not used, these pins can be floating (i.e., no connect) or be connected to v cc . 42 5u tdo output ieee 1149.1 test output : lvttl-level output. if serial boundary scan (jtag) is not used, these pins can be floating (i.e., no connect). 14, 15, 16, 41, 65, 66, 91 4c, 2j, 4j, 6j, 4r, 5r v cc supply power supply : +3.3v ? 5% and +5%. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 3d, 5d, 3e, 5e, 3f, 5f, 3h, 5h, 3k, 5k, 3m, 5m, 3n, 5n, 3p, 5p v ss ground ground : gnd. 4, 11, 20, 27, 54, 61, 70, 77 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u v ccq i/o supply output buffer supply : +3.3v ? 0.165v and +0.165v for 3.3v i/o. +2.5v ? 0.125v and +0.4v for 2.5v i/o. 84 4a, 1b, 7b, 1c, 7c, 4d, 3j, 5j, 4l, 1r, 7r, 1t, 2t, 6t, 6u nc ? no connect : these signals are not internally connected. it can be left floating or be connected to v cc or to gnd. pin descriptions ? 256k 36 (continued) 256k 36 tqfp pins 256k 36 pbga pins pin name type pin description pin descriptions ? 512k 18 512k 18 tqfp pins 512k 18 pbga pins pin name type pin description 37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 83, 99, 100 4p 4n 2a, 3a, 5a, 6a, 3b, 5b, 6b, 2c, 3c, 5c, 6c, 4g, 2r, 6r, 2t, 3t, 5t, 6t a0, a1, a input- synchronous synchronous address inputs : the address register is triggered by a combination of the rising edge of clk, adv/ld low, cen low, and true chip enables. a0 and a1 are the two least significant bits of the address field and set the internal burst counter if burst cycle is initiated. 93, 94, 5l 3g bwa , bwb input- synchronous synchronous byte write enables : each nine-bit byte has its own active low byte write enable. on load write cycles (when wen and adv/ld are sampled low), the appropriate byte write signal (bwx ) must be valid. the byte write signal must also be valid on each cycle of a burst write. byte write signals are ignored when wen is sampled high. the appropriate byte(s) of data are written into the device two cycles later. bwa controls dqa pins; bwb controls dqb pins. bwx can all be tied low if always doing write to the entire 18-bit word. 87 4m cen input- synchronous synchronous clock enable input : when cen is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. the effect of cen sampled high on the device outputs is as if the low-to-high clock transition did not occur. for normal operation, cen must be sampled low at rising edge of clock.
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 7 of 31 88 4h wen input- synchronous read write : wen signal is a synchronous input that identifies whether the current loaded cycle and the subsequent burst cycles initiated by adv/ld is a read or write operation. the data bus activity for the current cycle takes place two clock cycles later. 89 4k clk input- synchronous clock : this is the clock input to cy7c1356a/gvt71512zc18. except for oe , zz, and mode, all timing references for the device are made with respect to the rising edge of clk. 98, 92 4e, 6b ce , ce 3 input- synchronous synchronous active low chip enable : ce and ce 3 are used with ce 2 to enable the cy7c1356a/gvt71512zc18. ce or ce 3 sampled high or ce 2 sampled low, along with adv/ld low at the rising edge of clock, initiates a deselect cycle. the data bus will be high-z two clock cycles after chip deselect is initiated. 97 2b ce 2 input- synchronous synchronous active high chip enable : ce 2 is used with ce and ce 3 to enable the chip. ce 2 has inverted polarity but otherwise is identical to ce and ce 3 . 86 4f oe input asynchronous output enable : oe must be low to read data. when oe is high, the i/o pins are in high-impedance state. oe does not need to be actively controlled for read and write cycles. in normal operation, oe can be tied low. 85 4b adv /ld input- synchronous advance/load : adv/ld is a synchronous input that is used to load the internal registers with new address and control signals when it is sampled low at the rising edge of clock with the chip is selected. when adv/ld is sampled high, then the internal burst counter is advanced for any burst that was in progress. the external addresses and wen are ignored when adv/ld is sampled high. 31 3r mod e input- static burst mode : when mode is high or nc, the interleaved burst sequence is selected. when mode is low, the linear burst sequence is selected. mode is a static dc input. 64 7t zz input- asynchronou s sleep enable : this active high input puts the device in low power consumption standby mode. for normal operation, this input has to be either low or nc. 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 (a) 6d, 7e, 6f, 7g, 6h, 7k, 6l, 6n, 7p (b) 1d, 2e, 2g, 1h, 2k, 1l, 2m, 1n, 2p dqa dqb input/ output data inputs/outputs : both the data input path and data output path are registered and triggered by the rising edge of clk. byte ? a ? is dqa pins; byte ? b ? is dqb pins. 38 39 43 2u 3u 4u tms tdi tck input ieee 1149.1 test inputs : lvttl-level inputs. if serial boundary scan (jtag) is not used, these pins can be floating (i.e., no connect) or be connected to v cc . 42 5u tdo output ieee 1149.1 test inputs : lvttl-level output. if serial boundary scan (jtag) is not used, these pins can be floating (i.e., no connect). 14, 15, 16, 41, 65, 66, 91 4c, 2j, 4j, 6j, 4r, 5r v cc supply power supply : +3.3v ? 5% and +5%. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 3d, 5d, 3e, 5e, 3f, 5f, 5g, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5p v ss ground ground : gnd. pin descriptions ? 512k 18 (continued) 512k 18 tqfp pins 512k 18 pbga pins pin name type pin description
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 8 of 31 notes: 2. l means logic low. h means logic high. x means don ? t care. 3. multiple bytes may be selected during the same cycle. 4. bwc and bwd apply to 256k 36 device only. 5. upon completion of the burst sequence, the counter wraps around to its initial state and continues counting. 4, 11, 20, 27, 54, 61, 70, 77 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u v ccq i/o supply output buffer supply : +3.3v ? 0.165v and +0.165v for 3.3v i/o. +2.5v ? 0.125v and +0.4v for 2.5v i/o. 1-3, 6, 7, 25, 28-30, 51-53, 56, 57, 75, 78, 79, 84, 95, 96 4a, 1b, 7b, 1c, 7c, 2d, 4d, 7d, 1e, 6e, 2f, 1g, 6g, 2h, 7h, 3j, 5j, 1k, 6k, 2l, 4l, 7l, 6m, 2n, 7n, 1p, 6p, 1r, 7r, 1t, 4t, 6u nc ? no connect : these signals are not internally connected. it can be left floating or be connected to v cc or to gnd. pin descriptions ? 512k 18 (continued) 512k 18 tqfp pins 512k 18 pbga pins pin name type pin description partial truth table for read/write [2] function wen bwa bwb bwc [4] bwd [4] read h x x x x no write lhhhh write byte a (dqa) [3] llhhh write byte b (dqb) [3] lhlhh write byte c (dqc) [3] lhhlh write byte d (dqd} [3] lhhhl write all bytes l l l l l interleaved burst address table (mode = v cc or nc) first address (external) second address (internal) third address (internal) fourth address (internal) [5] a...a 00 a...a 01 a...a 10 a...a 11 a...a 01 a...a 00 a...a 11 a...a 10 a...a 10 a...a 11 a...a 00 a...a 01 a...a 11 a...a 10 a...a 01 a...a 00 linear burst address table (mode = v ss ) first address (external) second address (internal) third address (internal) fourth address (internal) [5] a...a 00 a...a 01 a...a 10 a...a 11 a...a 01 a...a 10 a...a 11 a...a 00 a...a 10 a...a 11 a...a 00 a...a 01 a...a 11 a...a 00 a...a 01 a...a 10
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 9 of 31 sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ? sleep ? mode. two clock cycles are required to enter into or exit from this ? sleep ? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ? sleep ? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ? sleep ? mode. ce s must remain inactive for the duration of t zzrec after the zz input returns low. cen needs to active before going into the zz mode and before you want to come back out of the zz mode. notes: 6. this assumes that cen , ce , ce 2 and ce 3 are all true. 7. all addresses, control and data-in are only required to meet set-up and hold time with respect to the rising edge of clock. d ata out is valid after a clock-to-data delay from the rising edge of clock. 8. dqc and dqd apply to 256k 36 device only. 9. l means logic low. h means logic high. x means don ? t care. high-z means high impedance. bwx = l means [bwa *bwb *bwc *bwd ] = low. bwx =h means [bwa *bwb *bwc *bwd ] = high. bwc and bwd apply to 256k 36 device only. 10. ce = h means ce and ce 3 are low along with ce 2 high. ce = l means ce or ce 3 are high or ce 2 is low. ce = x means ce , ce 3 , and ce 2 are don ? t care. 11. bwa enables write to byte ? a ? (dqa pins). bwb enables write to byte ? b ? (dqb pins). bwc enables write to byte ? c ? (dqc pins). bwd enables write to byte ? d ? (dqd pins). dqc, dqd, bwc , and bwd apply to 256k 36 device only. 12. the device is not in sleep mode, i.e., the zz pin is low. 13. during sleep mode, the zz pin is high and all the address pins and control pins are ? don ? t care. ? the snooze mode can only be entered two cycles after the write cycle, otherwise the write cycle may not be completed. 14. all inputs, except oe , zz, and mode pins, must meet set-up time and hold time specification against the clock (clk) low-to-high transition edge. 15. oe may be tied to low for all the operation. this device automatically turns off the output driver during write cycle. 16. device outputs are ensured to be in high-z during device power-up. 17. this device contains a two-bit burst counter. the address counter is incremented for all continue burst cycles. address wrap s to the initial address every fourth burst cycle. 18. continue burst cycles, whether read or write, use the same control signals. the type of cycle performed, read or write, depe nds upon the wen control signal at the begin burst cycle. a continue deselect cycle can only be entered if a deselect cycle is executed first. 19. dummy read and abort write cycles can be entered to set up subsequent read or write cycles or to increment the burst counter . 20. when an ignore clock edge cycle enters, the output data (q) will remain the same if the previous cycle is read cycle or rema in high-z if the previous cycle is write or deselect cycle. zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 10 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns truth table [9, 10, 11, 12, 13, 14, 15, 16, 17] operation previous cycle address used wen adv/ld ce cen bwx oe dq (2 cycles later) deselect cycle x x x l h l x x high-z continue deselect/nop [18] deselect x x h x l x x high-z read cycle (begin burst) x external h l l l x x q read cycle (continue burst) [18] read next x h x l x x q dummy read (begin burst) [19] x external h l l l x h high-z dummy read (continue burst) [18, 19] read next x h x l x h high-z write cycle (begin burst) x external l l l l l x d write cycle (continue burst) [18] write next x h x l l x d abort write (begin burst) [19] x external l l l l h x high-z abort write (continue burst) [18, 19] write next x h x l h x high-z ignore clock edge/nop [20] xxxhxhxx ?
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 10 of 31 ieee 1149.1 serial boundary scan (jtag) overview this device incorporates a serial boundary scan access port (tap). this port is designed to operate in a manner consistent with ieee standard 1149.1-1990 (commonly referred to as jtag), but does not implement all of the functions required for ieee 1149.1 compliance. certain functions have been modified or eliminated because their implementation places extra delays in the critical speed path of the device. never- theless, the device supports the standard tap controller archi- tecture (the tap controller is the state machine that controls the taps operation) and can be expected to function in a manner that does not conflict with the operation of devices with ieee standard 1149.1 compliant taps. the tap operates using lvttl/lvcmos logic level signaling. disabling the jtag feature it is possible to use this device without using the jtag feature. to disable the tap controller without interfering with normal operation of the device, tck should be tied low (v ss ) to prevent clocking the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be pulled up to v cc through a resistor. tdo should be left unconnected. upon power-up the device will come up in a reset state which will not interfere with the operation of the device. test access port tck ? test clock (input) clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms ? test mode select (input) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. tdi ? test data in (input) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to figure 1 , tap controller state diagram). it is allowable to leave this pin unconnected if it is not used in an application. the pin is pulled up internally, resulting in a logic high level. tdi is connected to the most significant bit (msb) of any register (see figure 2 ). tdo ? test data out (output) the tdo output pin is used to serially clock data-out from the registers. the output that is active depending on the state of the tap state machine (refer to figure 1 , tap controller state diagram). output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. tdo is connected to the lsb of any register (see figure 2 ). performing a tap reset the tap circuitry does not have a reset pin (trst , which is optional in the ieee 1149.1 specification). a reset can be performed for the tap controller by forcing tms high (v cc ) for five rising edges of tck and pre-loads the instruction register with the idcode command. this type of reset does not affect the operation of the system logic. the reset affects test logic only. at power-up, the tap is reset internally to ensure that tdo is in a high-z state. tap registers overview the various tap registers are selected (one at a time) via the sequences of ones and zeros input to the tms pin as the tck is strobed. each of the tap registers is a serial shift register that captures serial input data on the rising edge of tck and pushes serial data out on subsequent falling edge of tck. when a register is selected, it is connected between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run test/idle or the various data register states. the instructions are three bits long. the register can be loaded when it is placed between the tdi and tdo pins. the parallel outputs of the instruction register are automatically preloaded with the idcode instruction upon power-up or whenever the controller is placed in the test-logic reset state. when the tap controller is in the capture-ir state, the two least significant bits of the serial instruction register are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board-level serial test data path. bypass register the bypass register is a single-bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the device tap to another device in the scan chain with minimum delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional i/o pins (not counting the tap pins) on the device. this also includes a number of nc pins that are reserved for future needs. there are a total of 70 bits for x36 device and 51 bits for x18 device. the boundary scan register, under the control of the tap controller, is loaded with the contents of the device i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. the extest, sample/ preload and sample-z instructions can be used to capture the contents of the i/o ring. the boundary scan order table describes the order in which the bits are connected. the first column defines the bit ? s position in the boundary scan register. the msb of the register is connected to tdi, and lsb is connected to tdo. the second column is the signal name and the third column is the bump number. the third column is the tqfp pin number and the fourth column is the bga bump number.
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 11 of 31 identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the device as described in the identification register definitions table. tap controller instruction set overview there are two classes of instructions defined in the ieee standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. some public instructions are mandatory for ieee 1149.1 compliance. optional public instructions must be implemented in prescribed ways. although the tap controller in this device follows the ieee 1149.1 conventions, it is not ieee 1149.1 compliant because some of the mandatory instructions are not fully implemented. the tap on this device may be used to monitor all input and i/o pads, but can not be used to load address, data, or control signals into the device or to preload the i/o buffers. in other words, the device will not perform ieee 1149.1 extest, intest, or the preload portion of the sample/preload command. when the tap controller is placed in capture-ir state, the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shift-ir state the instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction sets for this device are listed in the following tables. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in this device. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the device responds as if a sample/preload instruction has been loaded. there is one difference between two instruc- tions. unlike sample/preload instruction, extest places the device outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in the instruction upon power-up and at any time the tap controller is placed in the test-logic reset state. sample-z if the high-z instruction is loaded in the instruction register, all output pins are forced to a high-z state and the boundary scan register is connected between tdi and tdo pins when the tap controller is in a shift-dr state. sample/preload sample/preload is an ieee 1149.1 mandatory instruction. the preload portion of the command is not implemented in this device, so the device tap controller is not fully ieee 1149.1-compliant. when the sample/preload instruction is loaded in the instruction register and the tap controller is in the capture-dr state, a snap shot of the data in the device ? s input and i/o buffers is loaded into the boundary scan register. because the device system clock(s) are independent from the tap clock (tck), it is possible for the tap to attempt to capture the input and i/o ring contents while the buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results can not be expected. to guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the tap controller ? s capture set-up plus hold time (t cs plus t ch ). the device clock input(s) need not be paused for any other tap operation except capturing the input and i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo pins. because the preload portion of the command is not imple- mented in this device, moving the controller to the update-dr state with the sample/preload instruction loaded in the instruction register has the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap controller is in the shift-dr state, the bypass register is placed between tdi and tdo. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. reserved do not use these instructions. they are reserved for future use.
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 12 of 31 note: 21.the ? 0 ? / ? 1 ? next to each state represents the value at tms at the rising edge of tck. figure 1. tap controller state diagram [21] test-logic reset reun-test/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 13 of 31 figure 2. tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . x 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tdi tdi [22] tap electrical characteristics (20 c < t j < 110 c; v cc = 3.3v ? 0.2v and +0.3v unless otherwise noted) parameter description test conditions min. max. unit v ih input high (logic 1) voltage [23, 24] 2.0 v cc + 0.3 v v il input low (logic 0) voltage [23, 24] ? 0.3 0.8 v il i input leakage current 0v < v in < v cc ? 5.0 5.0 a il i tms and tdi input leakage current 0v < v in < v cc ? 30 30 a il o output leakage current output disabled, 0v < v in < v ccq ? 5.0 5.0 a v olc lvcmos output low voltage [23, 25] i olc = 100 a 0.2 v v ohc lvcmos output high voltage [23, 25] i ohc = 100 a v cc ? 0.2 v v olt lvttl output low voltage [23] i olt = 8.0 ma 0.4 v v oht lvttl output high voltage [23] i oht = 8.0 ma 2.4 v notes: 22. x = 69 for the x36 configuration; x = 50 for the x18 configuration. 23. all voltage referenced to v ss (gnd). 24. overshoot: v ih (ac) < v cc + 1.5v for t < t khkh /2; undershoot: v il (ac) < ? 0.5v for t < t khkh /2; power-up: v ih < 3.6v and v cc < 3.135v and v ccq < 1.4v for t< 200 ms. during normal operation, v ccq must not exceed v cc . control input signals (such as wen and adv/ld ) may not have pulse widths less than t khkl (min.). 25. this parameter is sampled.
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 14 of 31 tap ac switching characteristics over the operating range [26, 27] parameter description min. max. unit clock t thth clock cycle time 20 ns f tf clock frequency 50 mhz t thtl clock high time 8 ns t tlth clock low time 8 ns output times t tlqx tck low to tdo unknown 0 ns t tlqv tck low to tdo valid 10 ns t dvth tdi valid to tck high 5 ns t thdx tck high to tdi invalid 5 ns set-up times t mvth tms set-up 5 ns t tdis tdi set-up 5 ns t cs capture set-up 5 ns hold times t thmx tms hold 5 ns t tdih tdi hold 5 ns t ch capture hold 5 ns notes: 26. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 27. test conditions are specified using the load in tap ac test conditions.
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 15 of 31 tap timing and test conditions test clock (tck) t thth t thtl t tlth test mode select (tms) test data in (tdi) test data out (tdo) t mvth t thmx t dvth t thdx t tlqx t tlqv (a) tdo c l = 20 pf z 0 = 50 ? gnd 1.5v 50 ? 3.0v v ss all input pulses 1.5v 1.5 ns 1.5 ns identification register definitions instruction field 256k x 36 512k x 18 description revision number(31:28) xxxx xxxx reserved for revision number. device depth (27:23) 00110 00111 defines depth of 256k or 512k words. device width (22:18) 00100 00011 defines width of x36 or x18 bits. reserved (17:12) xxxxxx xxxxxx reserved for future use. cypress jedec id code (11:1) 00011100100 00011100100 allows unique identification of device vendor. id register presence indicator (0) 1 1 indicates the presence of an id register. scan register sizes register name bit size (x36) bit size (x18) instruction 3 3 bypass 1 1 id 32 32 boundary scan 70 51
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 16 of 31 instruction codes instruction code description extest 000 captures i/o ring contents . places the boundary scan register between tdi and tdo. forces all device outputs to high-z state. this instruction is not ieee 1149.1-compliant. idcode 001 preloads id register with vendor id code and places it between tdi and tdo . this instruction does not affect device operations. sample-z 010 captures i/o ring contents . places the boundary scan register between tdi and tdo. forces all device outputs to high-z state. reserved 011 do not use these instructions ; they are reserved for future use. sample/preload 100 captures i/o ring contents . places the boundary scan register between tdi and tdo. this instruction does not affect device operations. this instruction does not implement ieee 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use these instructions ; they are reserved for future use. reserved 110 do not use these instructions ; they are reserved for future use. bypass 111 places the bypass register between tdi and tdo . this instruction does not affect device operations.
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 17 of 31 boundary scan order (256k 36) bit# signal name tqfp bump id 1 a 44 2r 2a453t 3a464t 4a475t 5 a 48 6r 6 a 49 3b 7 a 50 5b 8 dqa 51 6p 9 dqa 52 7n 10dqa536m 11 dqa 56 7l 12 dqa 57 6k 13 dqa 58 7p 14 dqa 59 6n 15 dqa 62 6l 16 dqa 63 7k 17 zz 64 7t 18 dqb 68 6h 19 dqb 69 7g 20 dqb 72 6f 21 dqb 73 7e 22 dqb 74 6d 23 dqb 75 7h 24 dqb 78 6g 25 dqb 79 6e 26 dqb 80 7d 27 a 81 6a 28 a 82 5a 29 a 83 4g 30 nc 84 4a 31 adv/ld 85 4b 32 oe 86 4f 33 cen 87 4m 34 wen 88 4h 35 clk 89 4k 36 ce 3 92 6b 37 bwa 93 5l 38 bwb 94 5g 39 bwc 95 3g 40 bwd 96 3l 41 ce 2 97 2b 42 ce 98 4e 43 a 99 3a 44 a 100 2a 45 dqc 1 2d 46 dqc 2 1e 47 dqc 3 2f 48 dqc 6 1g 49 dqc 7 2h 50 dqc 8 1d 51 dqc 9 2e 52 dqc 12 2g 53 dqc 13 1h 54 nc 14 5r 55 dqd 18 2k 56 dqd 19 1l 57 dqd 22 2m 58 dqd 23 1n 59 dqd 24 2p 60 dqd 25 1k 61 dqd 28 2l 62 dqd 29 2n 63 dqd 30 1p 64 mode 31 3r 65 a 32 2c 66 a 33 3c 67 a 34 5c 68 a 35 6c 69 a1 36 4n 70 a0 37 4p boundary scan order (256k 36) bit# signal name tqfp bump id
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 18 of 31 boundary scan order (512k 18) bit# signal name tqfp bump id 1 a 44 2r 2a452t 3a463t 4a475t 5 a 48 6r 6 a 49 3b 7 a 50 5b 8 dqa 58 7p 9 dqa 59 6n 10 dqa 62 6l 11 dqa 63 7k 12 zz 64 7t 13 dqa 68 6h 14 dqa 69 7g 15 dqa 72 6f 16 dqa 73 7e 17 dqa 74 6d 18 a 80 6t 19 a 81 6a 20 a 82 5a 21 a 83 4g 22 nc 84 4a 23 adv/ld 85 4b 24 oe 86 4f 25 cen 87 4m 26 wen 88 4h 27 clk 89 4k 28 ce 3 92 6b 29 bwa 93 5l 30 bwb 94 3g 31 ce 2 97 2b 32 ce 98 4e 33 a 99 3a 34 a 100 2a 35 dqb 8 1d 36 dqb 9 2e 37 dqb 12 2g 38 dqb 13 1h 39 nc 14 5r 40 dqb 18 2k 41 dqb 19 1l 42 dqb 22 2m 43 dqb 23 1n 44 dqb 24 2p 45 mode 31 3r 46 a 32 2c 47 a 33 3c 48 a 34 5c 49 a 35 6c 50 a1 36 4n 51 a0 37 4p boundary scan order (512k 18) bit# signal name tqfp bump id
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 19 of 31 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) voltage on v cc supply relative to v ss ......... ? 0.5v to +4.6v v in ........................................................... ? 0.5v to v cc +0.5v storage temperature (plastic) ...................... ? 55 c to +125 junction temperature ..................................................+125 power dissipation .........................................................2.0w short circuit output current ....................................... 50 ma static discharge voltage ......................................... > 2001v (per mil-std-883, method 3015) latch-up current ................................................... > 200 ma operating range range ambient temperature [28] v cc v ccq commercial 0 c to +70 c 3.3v 5% 2.5v-5%/ 3.3v+10% industrial -40 c to +85 c electrical characteristics over the operating range parameter description test conditions min. max. unit v ihd input high (logic 1) voltage [23, 29] all other inputs 2.0 v cc + 0.3 v v ih 3.3v i/o 2.0 v 2.5v i/o 1.7 v v il input low (logic 0) voltage [23, 29] 3.3v i/o ? 0.3 0.8 v 2.5v i/o ? 0.3 0.7 v il i input leakage current 0v < v in < v cc - 5 a il i mode and zz input leakage current [30] 0v < v in < v cc - 30 a il o output leakage current output(s) disabled, 0v < v out < v cc - 5 a v oh output high voltage [23] i 0h = ? 5.0 ma for 3.3v i/o 2.4 v i 0h = ? 1.0 ma for 2.5v i/o 2.0 v v ol output low voltage [23] i 0l =8.0 ma for 3.3v i/o 0.4 v i 0l = 1.0 ma for 2.5v i/o 0.4 v v cc supply voltage [23] i 0h =1.0 ma 3.135 3.465 v v ccq i/o supply voltage [23] 3.3v i/o 3.135 3.465 v 2.5v i/o 2.375 2.9 v parameter description conditions typ. 200 mhz/ -5 166 mhz/ -6 133 mhz/ -7.5 100 mhz/ -10 unit i cc power supply current: operating [31, 32, 33, 34] device selected; all inputs < v il or > v ih ; cycle time > t kc min.; v cc =max.; outputs open, adv/ld = x, f = f max 2 200 560 480 410 350 ma i sb1 automatic ce power-down current ? ttl inputs device deselected; all inputs < v il or > v ih ; v cc = max.; clk cycle time > t kc min. ma i sb2 cmos standby [32, 33, 34] device deselected; v cc = max.; all inputs < v ss + 0.2 or > v cc ? 0.2; all inputs static; clk frequency = 0 15 30 30 30 30 ma i sb3 ttl standby [32, 33, 34] device deselected; all inputs < v il or > v ih ; all inputs static; v cc = max.; clk frequency = 0 20 50 50 50 50 ma i sb4 clock running [32, 33, 34] device deselected; all inputs < v il or > v ih ; v cc = max; clk cycle time > t kc min. 50 230 200 190 170 ma notes: 28. t a is the case temperature. 29. overshoot: v ih < +6.0v for t < t kc /2; undershoot: v il < ? 2.0v for t < t kc /2. 30. mode pin has an internal pull-up and zz pin has an internal pull-down. these two pins exhibit an input leakage current of 5 0 a. 31. i cc is given with no output current. i cc increases with greater output loading and faster cycle times. 32. ? device deselected ? means the device is in power-down mode as defined in the truth table. ? device selected ? means the device is active. 33. typical values are measured at 3.3v, 25 c, and 20-ns cycle time. 34. at f = f max , inputs are cycling at the maximum frequency of read cycles of 1/t cyc ; f = 0 means no input lines are changing.
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 20 of 31 capacitance [25] parameter description test conditions typ. max. unit c i input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 4 4 pf c i/o input/output capacitance (dq) 7 6.5 pf thermal resistance parameter description test conditions tqfp typ. unit ja thermal resistance (junction to ambient) still air, soldered on a 4.25 x 1.125 inch, 4-layer pcb 25 c/w jc thermal resistance (junction to case) 9 c/w dq 317 ? 351 ? 5pf (a) (b) dq 50 ? z 0 = 50 ? v t = 1.5v all input pulses 0v 90% 10% 90% 10% 1.0 ns 1.0 ns (c) v ccq v ccq ac test loads and waveforms switching characteristics over the operating range [17] parameter description -5/ 200 mhz -6/ 166 mhz -7.5/ 133 mhz -10/ 100 mhz unit min. max. min. max. min. max. min. max. clock t kc clock cycle time 5.0 6.0 7.5 10 ns t kh clock high time 1.8 2.1 2.6 3.5 ns t kl clock low time 1.8 2.1 2.6 3.5 ns output times t kq clock to output valid 3.2 3.6 4.2 5.0 ns t kqx clock to output invalid 1.0 1.0 1.0 1.0 ns t kqlz clock to output in low-z [25, 36, 37] 1.0 1.0 1.0 1.0 ns t kqhz clock to output in high-z [25, 36, 37] 1.0 3.0 1.0 3.0 1.0 3.0 1.0 3.0 ns t oeq oe to output valid 3.2 3.6 4.2 5.0 ns t oelz oe to output in low-z [25, 36, 37] 0 0 0 0 ns t oehz oe to output in high-z [25, 36, 37] 3.5 3.5 3.5 3.5 ns set-up times t s address and controls [38] 1.5 1.5 1.8 2.0 ns t sd data in [38] 1.5 1.5 1.8 2.0 ns hold times t h address and controls [38] 0.5 0.5 0.5 0.5 ns t hd data in [38] 0.5 0.5 0.5 0.5 ns notes: 35. test conditions as specified with the output loading as shown in (a) of ac test loads unless otherwise noted. 36. output loading is specified with c l =5 pf as in (a) of ac test loads. 37. at any given temperature and voltage condition, t kqhz is less than t kqlz and t oehz is less than t oelz . 38. this is a synchronous device. all synchronous inputs must meet specified set-up and hold time, except for ? don ? t care ? as defined in the truth table.
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 21 of 31 switching waveforms read timing [39, 40, 41, 42, 43] notes: 39. q(a 1 ) represents the first output from the external address a 1 . q(a 2 ) represents the first output from the external address a 2 ; q(a 2 +1) represents the next output data in the burst sequence of the base address a 2 , etc., where address bits a0 and a1 are advancing for the four word burst in the sequence defined by the state of the mode input. 40. ce 3 timing transitions are identical to the ce signal. for example, when ce is low on this waveform, ce 3 is low. ce 2 timing transitions are identical but inverted to the ce signal. for example, when ce is low on this waveform, ce 2 is high. 41. burst ends when new address and control are loaded into the sram by sampling adv/ld low. 42. wen is ? don ? t care ? when the sram is bursting (adv/ld sampled high). the nature of the burst access (read or write) is fixed by the state of the wen signal when new address and control are loaded into the sram. 43. bwc and bwd apply to 256k 36 device only. clk cke# r/w# address bwa#, bwb# ce# adv/ld# oe# dq a 1 a 2 q(a 1 ) q(a 2 ) q(a 2 +1) q(a 2 +2) q(a 2 +3) q(a 2 ) t kqlz t kqx t kq pipeline read burst pipeline read pipeline read t kqhz (cke# high , eliminates current l-h clock edge) (burst wraps around to initial state) t kl t kc t kh t s t h t s t s t s t s t h t h t h t h cen wen bw a, bw b, bw c, bw d ce oe adv/ld
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 22 of 31 write timing [40, 41, 42, 43, 44, 45] notes: 44. d(a 1 ) represents the first input to the external address a1. d(a 2 ) represents the first input to the external address a 2 ; d(a 2 + 1) represents the next input data in the burst sequence of the base address a 2 , etc., where address bits a0 and a1 are advancing for the four-word burst in the sequence defined by the state of the mode input. 45. individual byte write signals (bwx ) must be valid on all write and burst-write cycles. a write cycle is initiated when wen signal is sampled low when adv/ld is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. switching waveforms (continued) clk cke# r/w# address bwa#, bwb# ce# adv/ld# oe# dq a 1 a 2 d(a 1 ) d(a 2 ) d(a 2 +1) d(a 2 +2) d(a 2 +3) d(a 2 ) t sd t hd pipeline write burst pipeline write pipeline write (cke# high , eliminates current l-h clock edge) (burst wraps around to initial state) t kl t kc t kh t s t h bw(a 1 ) bw(a 2 ) bw(a 2 +1) bw(a 2 ) bw(a 2 +2) bw(a 2 +3) t s t s t s t s t s t h t h t h t h t h cen wen bw a, bw b, bw c, bw d ce oe adv/ld
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 23 of 31 read/write timing [40, 43, 45, 46] note: 46. q(a 1 ) represents the first output from the external address a 1 . d(a 2 ) represents the input data to the sram corresponding to address a 2 . switching waveforms (continued) clk cke# r/w# address bwa#, bwb# ce# adv/ld# oe# data in (d) a 1 a 2 write a 3 a 4 a 5 a 6 a 7 a 8 a 9 q(a 1 ) q(a 3 ) q(a 6 ) q(a 7 ) d(a 2 ) d(a 4 ) d(a 5 ) write data out (q) read read read t kq t kqhz t kqlz t kqx t kl t kc t kh bw(a 2 ) t s t h bw(a 4 ) bw(a 5 ) t s t s t s t s t s t h t h t h t h t h cen wen bw a, bw b, bw c, bw d ce oe adv/ld
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 24 of 31 cen timing [40, 43, 45, 46, 47] note: 47. cen when sampled high on the rising edge of clock will block that l-h transition of the clock from propagating into the sram . the part will behave as if the l-h clock transition did not occur. all internal registers in the sram will retain their previous states. switching waveforms (continued) clk cke# r/w# address bwa#, bwb# ce# adv/ld# oe# data in (d) a 1 a 2 t kl t kc t s t sd a 3 a 4 a 5 q(a 1 ) d(a 2 ) t hd data out (q) t kqx t kh t kqhz t kq t kqlz q(a 3 ) t h t s t s t s t s t s t h t h t h t h t h cen wen bw a, bw b, bw c, bw d ce oe adv/ld
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 25 of 31 ce timing [40, 43, 45, 48, 49] notes: 48. q(a 1 ) represents the first output from the external address a 1 . d(a 3 ) represents the input data to the sram corresponding to address a 3 , etc. 49. when either one of the chip enables (ce , ce 2 , or ce 3 ) is sampled inactive at the rising clock edge, a chip deselect cycle is initiated. the data-bus high-z one cycle after t switching waveforms (continued) clk cke# r/w# address bwa#, bwb# ce# adv/ld# oe# data in (d) a 1 a 2 t kl t kc t s t h t sd a 3 a 4 a 5 d(a 3 ) t hd data out (q) t kh t kqx t kqhz t kq t kqlz q(a 1 ) q(a 2 ) q(a 4 ) t oelz t oeq t oehz t s t s t s t s t s t h t h t h t h t h cen wen bw a, bw b, bw c, bw d ce oe adv/ld
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 26 of 31 notes: 50.device must be deselected when entering zz mode. see cycle descriptions table for all possible signal conditions to deselect the device. 51. i/os are in three-state when exiting zz sleep mode switching waveforms (continued) clk ce 1 ce 3 low high zz t zzs t zzrec i dd i dd (active) three-state i/os zz mode timing [ 50, 51] ce 2 i ddzz
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 27 of 31 ordering information speed (mhz) ordering code package name package type operating range 200 cy7c1354a-200ac/ gvt71256zc36-5 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial cy7c1354a-200bgc/ gvt71256zc36b-5 bg119 119-ball bga (14 x 22 x 2.4 mm) 166 cy7c1354a-166ac/ gvt71256zc36-6 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1354a-166bgc/ gvt71256zc36b-6 bg119 119-ball bga (14 x 22 x 2.4 mm) 133 cy7c1354a-133ac/ gvt71256zc36-7.5 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1354a-133bgc/ gvt71256zc36b-7.5 bg119 119-ball bga (14 x 22 x 2.4 mm) 100 cy7c1354a-100ac/ gvt71256zc36-10 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1354a-100bgc/ gvt71256zc36b-10 bg119 119-ball bga (14 x 22 x 2.4 mm) 200 cy7c1356a-200ac/ gvt71512zc18-5 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial cy7c1356a-200bgc/ gvt71512zc18 b-5 bg119 119-ball bga (14 x 22 x 2.4 mm) 166 cy7c1356a-166ac/ gvt71512zc18-6 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1356a-166bgc/ gvt71512zc18b-6 bg119 119-ball bga (14 x 22 x 2.4 mm) 133 cy7c1356a-133ac/ gvt71512zc18-7.5 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1356a-133bgc/ gvt71512zc18b-7.5 bg119 119-ball bga (14 x 22 x 2.4 mm) 100 cy7c1356a-100ac/ gvt71512zc18-10 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1356a-100bgc/ gvt71512zc18b-10 bg119 119-ball bga (14 x 22 x 2.4 mm)
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 28 of 31 ordering information speed (mhz) ordering code package name package type operating range 166 cy7c1354a-166aci/ gvt71256zc36-6 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack industrial cy7c1354a-166bgci/ gvt71256zc36b-6i bg119 119-ball bga (14 x 22 x 2.4 mm) 133 cy7c1354a-133aci/ gvt71256zc36-7.5i a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1354a-133bgci/ gvt71256zc36b-7.5i bg119 119-ball bga (14 x 22 x 2.4 mm) 100 cy7c1354a-100aci/ gvt71256zc36-10i a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1354a-100bgci/ gvt71256zc36b-10i bg119 119-ball bga (14 x 22 x 2.4 mm) 200 cy7c1356a-200aci/ GVT71512ZC18-5I a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1356a-200bgci/ gvt71512zc18 b-5i bg119 119-ball bga (14 x 22 x 2.4 mm) 166 cy7c1356a-166aci/ gvt71512zc18-6i a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1356a-166bgci/ gvt71512zc18b-6i bg119 119-ball bga (14 x 22 x 2.4 mm) 133 cy7c1356a-133aci/ gvt71512zc18-7.5i a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1356a-133bgci/ gvt71512zc18b-7.5i bg119 119-ball bga (14 x 22 x 2.4 mm) 100 cy7c1356a-100aci gvt71512zc18-10i a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1356a-100bgci/ gvt71512zc18b-10i bg119 119-ball bga (14 x 22 x 2.4 mm)
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 29 of 31 package diagrams 100-lead thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 30 of 31 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. no bus latency and nobl are trademarks of cypress semiconductor corporation. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 51-85115-*a 119-lead bga (14 x 22 x 2.4) bg119
cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 document #: 38-05161 rev. *b page 31 of 31 document title: cy7c1354a/gvt71256zc36 cy7c1356a/gvt71512zc18 256k x 36/512k x 18 pipelined sram with nobl ? architecture document number: 38-05161 rev. ecn no. issue date orig. of change description of change ** 3000 4/21/00 cxv new data sheet *a 114095 03/12/02 glc 1) updated v ih , v il , separate v ih and v il for 3.3v and 2.5v i/o. *b 114095 05/30/02 glc 1) added ? i ? temp 2) added automatic power down to features. 3) added zz mode to characteristics. 4) added zz mode timing waveform. 5) changed nomenclature for i sb . 6) updated latch-up current. 7) added static discharge voltage.

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